Static memory cells in certain environments in which radiation is present such as communication satellite orbital space are, or will likely be, particularly susceptible to soft errors or single event upsets (SEUs). A soft error or single event upset is typically caused by electron-hole pairs created by, and along the path of, a single energetic particle as it passes through an integrated circuit, such as a memory. The charge collected from this ion track will perturb the voltage of the struck node. If the struck node is in a memory cell, and the changed logic state persists longer than the time required to latch a new state in that memory cell (i.e., if the restoration time is longer than the latch time) the cell will be upset. This condition is generally expressed in terms of the critical charge. Should the charge collected from the ionized trail of an energetic particle through a critical volume of the memory cell exceed a critical charge then the logic state of the memory is upset. This critical charge, by definition, is the minimum amount of electrical charge required to change the logic state of the memory cell.
The energetic particle causing the ionization trail may be a cosmic ray or it may be an alpha particle (helium nucleus) such as alpha particles which may be emitted from standard integrated circuit packages for example.
One method for hardening a memory cell against SEU is by reducing the amount of charge generated by a given event. This is accomplished, for example, by using a silicon film thinner than the collection depth in the bulk material. For instance, a memory cell created on an insulator, such as in a SOI (silicon on insulator) device, is less susceptible to SEU than one created on bulk semiconductor, such as silicon, because ionization charge along a path in an insulator is more likely to recombine than be collected compared to ionization charge created in a semiconductor.
Another way to reduce the susceptibility of a memory cell to upset is by increasing the critical charge of the cell. One approach to improving the SEU rate based on increasing the critical charge is to increase the capacitance on the inverter drains, thus decreasing the voltage change on the node for a given amount of collected charge. The effectiveness of the capacitance in increasing the critical charge for SEU is increased by having the capacitance from the drain to the gate of the same inverter to get the benefit of the Miller effect. Still, the area required for a sufficiently large capacitor makes this undesirable for high levels of SEU resistance.
Another hardening scheme against SEU in static memory cells based on critical charge required to produce SEU is accomplished by increasing the feedback time of the latch, thus allowing more time for the restoration current to restore the original state of the memory cell before the upset state is latched. This can be accomplished by including resistors in the cross coupling lines of the two cross coupled inverters which comprise the memory cell. However, this approach of increasing the RC propagation delay also significantly slows the write cycle time of the cell. In addition, it is difficult to control the values of the resistors at the levels necessary for this feedback approach. Therefore, this resistive approach to SEU hardening is no longer desirable.
The improvement in SEU response of a memory cell by increasing the RC delay of the feedback can be accomplished by increasing the capacitance; however, the write speed will also be negatively impacted in this case. In addition, generally, added capacitance will take up more room than increasing the resistivity of the resistor. Therefore, adding capacitance to increase RC delay of the feedback has not been a preferred approach.
Another method used to increase SEU hardness is to include a pair of transistors connected in the cross coupling of the inverters. This method is non optimal, however, because it requires a larger area than would currently be desired.
Accordingly, improvements which overcome any or all of the problems are presently desirable.